The present invention pertains in general to the fabrication of semiconductor devices and, in particular, to self-aligned methods for manufacturing high density integrated circuits.
A recent advance in fabricating high density integrated circuits is the use of self-aligning techniques. These techniques use selectively etchable thin layers with openings in one layer forming the etching mask for openings in subsequent layers to form a given device region. In addition to the fundamental device region registration advantages offered by self-alignment, the use of multiple dielectric layers in a selective etching technique offers inherent protection against device defects caused by mask scars or pinholes. This pinhole protection derives from the fact that any pinholes in the upper dielectric layer caused by defects in the master mask will be covered by photoresists in the steps used to selectively "enable" selected groups of master mask openings in subsequent process steps.
In prior art process for fabricating transistors, multiple dielectric layers and selective etching have been used in conjunction with a single master mask to form collector contact, base contact and emitter regions which are self-aligned with respect to each other. These processes require preliminary masking steps to provide the required registration of isolation and buried layer regions, base and isolation regions and when required, the registration of a deep collector contact within the isolation region. With the advent of higher density integrated circuits and, in particular, with large memory and microprocessor integrated circuits having a large number of closely spaced devices, the registration of base and isolation regions becomes extremely critical. The yields of these type integrated circuits manufactured using prior art processes have suffered because this registration problem is not addressed. The yields of large, high density integrated circuits manufactured using prior art processes are also adversely affected by the fact that the pinhole protection inherent in self-alignment techniques is unavailable to preliminary masking steps and by the fact that the sequence of selective diffusion and reoxidation process steps required by a single master mask create additional dielectric layer transitions or "steps" across the upper surface of the integrated circuit. The loss of planarity associated with these "steps" makes it difficult to obtain reliable interconnecting metal patterns, especially in multilevel metallization systems.